1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, a semiconductor device manufacturing method including the step of forming wiring layers of a multilevel wiring structure and a via by using a dual damascene method.
2. Description of the Prior Art
In recent years, the width of the wiring is narrowed with the miniaturization of the semiconductor device and also the distance between the wirings becomes narrower. Therefore, wiring resistance is increased and also a parasitic capacitance due to the wirings is increased. This delays a signal speed and prevents a higher speed operation of the semiconductor device according to the scaling law.
Under such circumstances, in order to reduce the parasitic capacitance between the wirings and the wiring resistance, it is needed to check again the multilevel wiring forming method and the insulating material and the metal wiring material.
The insulating material with the small dielectric constant is effective to reduce the wiring capacitance. Also, selection of the metal wiring material is shifted from aluminum (Al) to copper (Cu) having the small resistivity to reduce the wiring resistance.
Because it is difficult to apply the conventional dry etching in working a copper film, the damascene method is employed to work the copper film. The damascene method can be roughly classified into the single damascene method and the dual damascene method.
According to the single damascene method, formation of the plug (via) used to connect the underlying wiring and the overlying wiring and formation of the wirings must be conducted by individual steps. According to the dual damascene method, the wirings and the plug can be formed simultaneously.
The multilayer structure of the wiring layers of the semiconductor device is advanced with the miniaturization. For example, the number of wirings comes up to six layers in the semiconductor device of 0.18 xcexcm wiring width generation. In this case, the wiring structure can be formed by repeating similar steps twelve times (six wiring formation steps and six plug formation steps), for example, according to the single damascene method, whereas the wiring structure can be formed only by repeating similar steps six times according to the dual damascene method.
The reason why the number of steps employed in the dual damascene method is merely half of the single damascene method is that, as described above, the wirings and the plug can be formed simultaneously. Hence, the dual damascene method is advantageous to suppress a production cost and to increase a production efficiency.
In addition, since the contact resistance between the underlying wiring and the plug connected to this wiring is low if the dual damascene method is employed, a failure in contact between them can be avoided easily and reliability of the wiring can be enhanced.
The dual damascene method is set forth in, for example, Patent Application Publication (KOKAI) Hei 9-55429 and Patent Application Publication (KOKAI) Hei 10-112503 in which the dual damascene method is applied to the interlayer insulating film including the low dielectric constant insulating film.
To begin with, steps of forming the copper plug and the copper wiring structure by the dual damascene method which is set forth in Patent Application Publication (KOKAI) Hei 9-55429 are shown in FIGS. 1A to 1D.
First, as shown in FIG. 1A, a first silicon oxide film 2, an organic low dielectric constant film 3, and a second silicon oxide film 4 are formed in sequence on a silicon substrate 1. In this case, fluorocarbon polymer such as polytetrafluoroethylene is employed as material of the organic low dielectric constant film. Then, an opening 4a having a wiring profile is formed in the second silicon oxide film 4 by patterning the second silicon oxide film 4. Then, as shown in FIG. 1B, resist is formed on the second silicon oxide film 4 and the opening 4a. A plug window 5a is formed on a part of the opening 4a by exposing/developing the resist. The resultant resist is employed as a resist pattern 5. Then, as shown in FIG. 1C, a via-hole 6 is formed by etching the organic low dielectric constant film 3 and the first silicon oxide film 2 in sequence through the plug window 5a of the resist pattern 5. Then, as shown in FIG. 1D, a wiring recess 7 is formed by selectively etching the organic low dielectric constant film 3 by the oxygen plasma through the opening 4a of the second silicon oxide film 4. Then, although not particularly shown, copper is buried in the via-hole 6 and the wiring recess 7, whereby the plug and the wiring are formed at the same time.
Next, steps of forming the copper plug and the copper wiring structure by the dual damascene method which is set forth in Patent Application Publication (KOKAI) Hei 10-112503 are shown in FIGS. 2A to 2C.
First, as shown in FIG. 2A, wiring recesses are formed in a silicon oxide film 12 formed on a semiconductor substrate 11, and then underlying wirings 13 are buried in the recesses. Then, a low dielectric constant resin film 14 and a first photoresist film 15 with low sensitivity are formed in sequence on the silicon oxide film 12 and the underlying wirings 13. Then, a hole latent image 15a in the first photoresist film 15 is formed by exposing. Then, a second photoresist film 16 with high sensitivity is coated on the first resist film 15. A latent image 16a of a wiring is then formed by exposing the second photoresist film 16. A part of the wiring latent image 16a is formed to overlap with the hole latent image 15a. Then, as shown in FIG. 2B, the first photoresist film 15 and the second photoresist film 16 are developed successively, so that the wiring latent image 16a is removed to form a wiring window 16b and also the hole latent image 15a is removed to form a hole window 15b. After this, the first photoresist film 15, the second photoresist film 16, and the low dielectric constant resin film 14 are etched sequentially from the upper side, as shown in FIG. 2C. As a result, a vertical contact hole 17 and a wiring recess 18 are formed in the low dielectric constant resin film 14. The copper (not shown) is buried in the vertical contact hole 17 and the wiring recess 18 simultaneously. Such copper is used as the plug in the vertical contact hole 17 and also used as the wiring in the wiring recess 18.
The above prior arts have a few problems as follows.
In the steps as shown in FIG. 1A, when the photoresist 8 used for a patterning mask is removed by the oxygen plasma, the organic low dielectric constant film 3 made of hydrocarbon resin under the second silicon oxide film 4 is etched into a wiring profile by the oxygen plasma. Therefore, pattern precision of the via-hole formed in the second silicon oxide film 4 is degraded. This is because chemical properties of the low dielectric constant organic material containing the hydrocarbon approximate the photoresist 8 and thus only the photoresist 8 cannot be removed selectively.
In this case, the reason why the hydrocarbon resin is employed as the organic low dielectric constant film is that the hydrocarbon resin is superior to the fluorocarbon polymer in adhesiveness for the silicon oxide film.
In addition, in the steps shown in FIGS. 2A to 2C, three different resin materials of the low dielectric constant resin film 14, the first photoresist film 15, and the second photoresist film 16 must be etched at the same etching rate. However, respective etching rates of these resin materials are different depending upon the width of the wiring recess 18 and the diameter of the vertical contact hole 17. Therefore, if the wiring recesses each having a different profile or width, or the vertical contact holes 17 each having a different diameter are to be formed in the same layer, it is difficult to etch these resin materials while controlling respective layers to coincide with their designed dimensions.
It is an object of the present invention to provide a semiconductor device manufacturing method including an interlayer insulating film patterning step which is able to form a wiring recess and a hole with good precision even when hydrocarbon resin is employed as a low dielectric constant film.
According to an aspect of the present invention, after a first insulating film, an organic insulating film, a second insulating film, and a metal film are formed in sequence over a substrate, an opening having a wiring pattern is formed in the metal film by the photolithography, then an opening having a via pattern profile is formed in the second insulating film by the photolithography, then the organic insulating film is etched using the second insulating film as a mask, then the first insulating film and the second insulating film are etched simultaneously while using the metal film and the organic insulating film as a mask, and then the organic insulating film is etched while using the second insulating film as a mask. At this stage, a wiring recess is formed in the organic insulating film and the second insulating film, and a via-hole is formed in the first insulating film.
Accordingly, since the organic insulating film can be protected by the second insulating film in removing the resist which is employed to form the opening in the metal film, the organic insulating film is never etched by the resist removing etchant.
In addition, when the underlying organic insulating film is etched by using the second insulating film as a mask, the resist on the second insulating film can be removed simultaneously with the etching of the organic insulating film. Thereby, there is no need that the resist should be removed solely, and the underlying organic insulating film which is exposed is not badly affected at all in removing the resist. Accordingly, the wiring recess and the via can be formed with high precision by applying not only fluorocarbon polymer but also hydrocarbon resin as constituent material of the organic insulating film.
Furthermore, since the first insulating film, the organic insulating film, and the second insulating film are sequentially etched under the optimum condition, the via-hole or the wiring recess can be formed in these films with high precision.
According to another aspect of the present invention, after the first insulating film, the organic insulating film, and the second insulating film are formed in sequence, an opening having a via pattern profile is formed in the second insulating film by the photolithography, then an opening having the via pattern profile is formed in the organic insulating film through the opening of the second insulating film, then an opening having a wiring pattern profile is formed in the second insulating film by the photolithography and at the same time an opening having the via pattern profile is formed by etching the first insulating film using the organic insulating film as a mask, and then an opening having the wiring pattern profile is formed by etching the organic insulating film while using the second insulating film as a mask.
In this manner, both the step of removing the resist used to form the opening and the step of forming the opening having the via pattern profile in the organic insulating film while using the second insulating film as a mask can be executed simultaneously by forming the opening having the via pattern profile in the second insulating film. Therefore, the patterning of the underlying organic insulating film into the unnecessary profile in removing the resist can be avoided. In addition, the organic insulating film is never etched into the unnecessary size in removing the resist formed on the second insulating film, so that the precision of the opening in the organic insulating film is never degraded.
Moreover, after the opening having the wiring pattern profile is formed in the second insulating film and then the opening having the via-hole profile is formed in the underlying organic insulating film, these opening profiles are transferred sequentially onto the insulating films positioned below them. Therefore, the wiring recess and the via-hole can be formed in the first insulating film, the second insulating film and the organic insulating film. As a result, the first insulating film, the second insulating film, and the organic insulating film can be etched individually under their optimum conditions, so that the wiring recess and the via-hole can be formed with high precision.
As described above, since it is possible to apply the dual damascene method to the multilevel wiring formation which employs the copper wiring and the low dielectric constant organic insulating film without selection of material for the organic insulating film, performance, reliability, and production efficiency of the semiconductor device can be improved.
The underlying organic insulating film may be interposed between the first insulating film and the second insulating film. The etching of the underlying organic insulating film may be carried out simultaneously when the overlying organic insulating film is etched.
According to still another aspect of the present invention, after the first insulating film and the second insulating film have been formed in sequence over the substrate, the opening having the via-hole pattern profile is formed in the first insulating film and the second insulating film by using the first photoresist, and then the opening having the wiring pattern profile is formed by etching the second insulating film and the upper portion of the first insulating film by using the second photoresist.
In this way, if the organic insulating material is adopted as the first insulating film, both the step of removing the resist used to form the opening and the step of forming the opening having the via pattern profile in the organic insulating film while using the second insulating film as a mask can be executed simultaneously by forming the opening having the via pattern profile in the second insulating film. Therefore, the first insulating film formed of the underlying organic insulating material is never etched into the unnecessary size in removing the first resist, so that the precision of the opening in the organic insulating film is never degraded.
Accordingly, when the dual damascene method is applied to the multilevel wiring formation which employs the copper wiring and the low dielectric constant organic insulating film without selection of organic insulating material constituting the first insulating film, performance, reliability, and production efficiency of the semiconductor device can be improved.
Furthermore, according to the present invention, since the via and the wirings are formed in the first insulating film formed of organic material, the wiring capacitance can be reduced effectively rather than the multilevel wiring structure in which the silicon oxide and the silicon nitride are employed. In addition, the exchange number of the etching gas which is employed to form the via-hole and the wiring recess in the insulating film can be reduced, and thus it is possible to form the multilevel wirings at low cost.